Sr Mask Design Engineer
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Job Description
Job Responsibilities:
• Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite
• Perform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices.
• Work at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame)
• Verify connectivity and design rules with Assura, Calibre, PVS
• Use QRC extraction to analyze and reduce noisy/sensitive coupling
• Use third party tools to analyze IR drops and p2p resistance
• Liaise closely with analog designers on specific circuit requirements, e.g. power, matching, sensitivity, latch-up, ESD, etc.
• Work with CAD and CAE engineers to improve processes or features
Requirements
Function: Engineering
Experience Level: Mid-Senior Level