Senior Staff Digital Engineer
Job Description
Renesas is seeking an experienced Senior Staff Digital Engineer to lead verification and evidence
development for control-loop features and functions in advanced digital power management products
used in AI, datacenter, and high-performance computing applications.
This role focuses on proving that specific control-loop features behave as intended across requirements,
behavioral models, digital implementation, analog interactions, simulation, emulation, bench validation,
and silicon.
The successful candidate will translate feature intent into measurable test plans, define clear pass/fail
criteria, develop reusable verification methods, and correlate results across engineering environments.
The role requires a strong understanding of digital control loops, mixed-signal behavior, power-system
dynamics, data analysis, and verification automation.
The ideal candidate combines hands-on control-loop expertise with disciplined verification and the
ability to identify and resolve differences between expected behavior, implementation results, and
measured performance.
WHY THIS ROLE MATTERS
Build clear, repeatable evidence that control-loop features and functions operate as intended.
Improve confidence in feature and architecture decisions by connecting requirements, models,
implementation, tests, and measured results.
Identify feature-level gaps and unexpected interactions before they become product or customer issues.
Create reusable verification methods that improve engineering quality and reduce repeated manual
testing.
KEY RESPONSIBILITIES
Lead verification and evidence development for digital control-loop features and functions.
Translate feature requirements and system intent into measurable verification plans, test scenarios, and
pass/fail criteria.
Verify control-loop behavior across operating conditions, configurations, limits, sequencing, and corner
cases.
Develop tests covering compensation, stability, bandwidth, transient response, latency, sampling,
quantization, saturation, limits, mode transitions, sensing behavior, telemetry, and feature interactions.
Correlate feature behavior across behavioral models, RTL, analog/mixed-signal simulation, emulation,
bench validation, and silicon measurements where applicable.
Evaluate interactions between digital loop functions and analog components, including sensing paths,
ADCs, DACs, references, PWM generation, timing paths, and power stages.
Produce clear verification evidence containing test conditions, configurations, metrics, plots, waveforms,
results, conclusions, and identified risks.
Develop reusable automation for parameter sweeps, corner testing, waveform analysis, regression
testing, and evidence generation.
Investigate discrepancies between expected feature behavior and results from simulation, emulation,
bench testing, or silicon.
Collaborate with systems, analog design, digital design, firmware, design verification, validation,
applications, and software/tool teams.
Identify missing requirements, test coverage, observability, or infrastructure needed to verify loop
features effectively.
Document test intent, assumptions, configurations, results, limitations, and residual risks clearly for
technical and leadership audiences.
Provide technical guidance and mentorship to engineers working on control-loop verification and
validation.
Requirements
Function: Engineering
Experience Level: Mid-Senior Level