Director, SoC Design Verification and Virtual Platform Quality

About the Opportunity

This role offers the opportunity to shape a differentiated verification strategy at the intersection of semiconductor Design Verification, SystemC modeling, Virtual Platforms, and pre-silicon software development.

This leader will define and execute a reuse-first verification strategy spanning SystemC transaction-level models, RTL, IP, subsystem, SoC, and platform-level validation. The objective is to create a traceable verification asset chain that grows from loosely timed SystemC models through approximately timed models and RTL, rather than rebuilding independent verification environments at each stage.

The position is part of Renesas’ Software First, Simulation First engineering organization. The team develops reusable SystemC/TLM models and integrated Virtual Platforms that enable software development, verification, validation, and product evaluation before silicon availability. Design Verification is the quality and release gate that ensures these virtual products faithfully represent the intended silicon behavior.

Key Responsibilities

• Define and drive the verification strategy for SystemC models, RTL designs, reusable IP, subsystems, SoCs, and Virtual Platforms.
• Lead and develop a global Design Verification organization, including verification leads, engineers, external partners, and project-specific teams.
• Establish a common verification architecture that supports reuse of test intent, stimulus, sequences, checkers, scoreboards, assertions, coverage models, and regression infrastructure across SystemC and RTL.
• Develop scalable SystemVerilog/UVM environments, including protocol adapters and TLM bridges that connect pin-level UVM interfaces to SystemC/TLM models.
• Establish functional-equivalence and timing-correlation methodologies between SystemC LT/AT models and RTL implementations.
• Define common verification plans, feature identifiers, test intent, functional and code coverage goals, closure criteria, maturity classifications, and sign-off requirements.
• Make verification sign-off an explicit release gate for customer- and software-facing Virtual Platform deliveries.
• Drive verification planning and execution from the IP level through subsystem, chip-top, SoC, and full-platform integration.
• Establish a risk-based verification approach that balances reusable UVM environments, Python/C++ tests, software-driven validation, formal techniques, and project schedules.
• Lead verification of configurable and parameterized IP models across supported configurations, interfaces, and operating modes.
• Build CI/CD-based regression systems for automated compilation, simulation, coverage collection, result analysis, release evidence, and quality reporting.
• Partner with architecture, RTL design, SystemC modeling, software, validation, methodology, and Product Group teams to define requirements and acceptance criteria.
• Lead complex debug and root-cause analysis across models, adapters, RTL, testbenches, firmware, and platform-level environments.
• Evaluate and adopt verification technologies that improve quality, reuse, coverage closure, simulation efficiency, and engineering productivity.
• Own staffing, organizational development, program planning, partner engagement, execution tracking, risks, dependencies, and executive reporting for the DV function.
Leadership Profile

The successful candidate will:

• Set a clear technical and organizational direction while maintaining delivery accountability.
• Balance verification rigor, reuse, schedule, risk, and business priorities.
• Build durable methodology without allowing methodology development to block critical product execution.
• Develop strong technical leaders and create clear accountability across IP, subsystem, SoC, and platform verification.
• Promote collaboration across RTL, SystemC, software, validation, architecture, and product organizations.
• Establish a culture of measurable quality, evidence-based sign-off, disciplined debug, automation, and continuous improvement.

Function: Manufacturing
Experience Level: Director