Design Verification Engineer
Prefer a full account with a password? Sign Up to Apply
Job Description
This role is responsible for pre-silicon verification of advanced 3D NAND designs, including UVM-based verification, functional coverage, assertions, mixed-signal modeling and simulation, debugging, and verification-flow automation.
Key responsibilities
• Create and maintain verification test plans based on design specifications.
• Develop UVM-based directed and constrained-random tests, debug simulation failures, and quickly identify design, testbench, or test issues.
• Define functional coverage models and perform coverage analysis and closure.
• Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification requirements.
• Develop, maintain, and enhance the UVM-based verification environment to support evolving design and verification requirements.
• Develop and maintain mixed-signal full-chip models and verification environments, including analog behavioral models, cell-level testbenches, and full-chip mixed-signal netlists and testbenches.
• Develop scripts and tools to automate verification workflows, regression execution, results processing, and data collection.
Requirements
Department: NAND Development
Function: Other
Experience Level: Not Applicable