Principal Design Verification Engineer

We are seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffer silicon.

This role will drive verification strategy and execution for complex digital designs, working closely with design teams to ensure functionality, performance, and product requirements are met. The ideal candidate brings deep semiconductor verification expertise with SystemVerilog and UVM. Previous DDR or memory experience is an advantage, but is not required.

This is an opportunity to take significant technical ownership while contributing to next-generation DDR6 technology.

Key Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff.
• Work closely with RTL and design engineers to ensure designs meet functional and performance requirements and are effectively verifiable.
• Analyze specifications, design implementation, and verification results to identify functional gaps and design issues.
• Drive debugging and resolution of complex verification failures.
• Develop scalable and reusable verification components, methodologies, and best practices.
• Identify and lead improvements in verification efficiency, quality, performance, and reuse.
• Participate in architecture, feasibility, design, and technical reviews.
• Provide technical guidance and mentorship to verification engineers.
• Serve as a technical expert for assigned verification methodologies and tools.
• Communicate verification progress, coverage, technical risks, and readiness to engineering leadership and project stakeholders.

Function: Engineering
Experience Level: Mid-Senior Level