HDD Servo Processing Subsystem Architecture Lead

We are seeking an experienced HDD Servo Processing Subsystem Architecture Lead to join our organization in San Jose, CA, United States. In this pivotal role, you will drive the strategic vision and execution of the servo real-time compute platform architecture—encompassing firmware architecture, instruction set architecture (ISA), and SoC microarchitecture—to enable next-generation HDD products with multiple concurrent data streams and multi-actuator control. You will be accountable for defining a coherent, scalable platform strategy that balances technical feasibility with economic viability across program schedules, power envelopes, and cost constraints.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Define and maintain a future-state servo real-time compute architecture and ISA that scales from single to multiple concurrent data streams and supports concurrent control of multiple actuators and heads, with explicit guidance to SoC and servo teams on power, area, and performance trade-offs
• Co-lead SoC microarchitecture decisions affecting servo compute, including core count and placement, memory hierarchy, interconnect design, and dynamic control accelerators, ensuring that FPGA prototype work and accelerator designs map cleanly into production-ready firmware and tools models
• Own servo compute resource management and budgeting, including instruction/data memory allocation, processor cycle and path-length limits, and regression thresholds; drive adherence through continuous integration practices to prevent late-stage resource conflicts
• Lead the co-design of firmware platform architecture, including core control-loop implementations, multi-cluster and multi-actuator orchestration, and cross-generation stability, ensuring deterministic real-time performance across multiple SoC generations
• Drive evolution of the servo compute tooling ecosystem—including internal compiler, real-time compute platform simulator, Renode-based system simulation, debug and diagnostics tools, and profiling/debug flows—to support multi-cluster, multi-stream characterization and debugging
• Coordinate across geographically distributed teams (servo firmware, SoC architecture/design, recording subsystem/algorithms, servo tools, manufacturing firmware, and test) to align platform decisions with program risk, schedules, yield, and customer experience objectives
• Deliver a major multi-stream and multi-actuator capability that meets control performance and power targets on a new SoC generation, demonstrating the viability of the defined architecture and ISA
• Analyze and optimize servo loop performance through modeling, simulation, and real-world validation using tools such as MATLAB and Simulink, with focus on multi-actuator control scenarios and high-bandwidth data paths
• Communicate technical concepts, architectural trade-offs, and strategic recommendations to senior management and cross-functional stakeholders, providing architectural guidance throughout the product development lifecycle

Function: Engineering
Experience Level: Director